1. Field of the Invention
The present invention relates generally to a semiconductor structure and process thereof, and more specifically to a semiconductor structure and process thereof that forms recesses in a substrate and a dual spacer.
2. Description of the Prior Art
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to the very deep sub micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue in the field. In order to improve device performance, crystal strain technology has been developed. By putting a strain on a semiconductor crystal, the speed at which charges move through that crystal is altered. Strain makes MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
Attempts have been made to develop a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) epitaxial structure or a silicon carbide (SiC) epitaxial structure disposed therebetween. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxy silicon structure due to the silicon germanium or silicon carbide epitaxial structure which has a larger or smaller lattice constant than silicon. As a result, the band structure alters, and the carrier mobility increases, which enhances the speed performance of the MOS transistors. Furthermore, the sizes, shapes of the epitaxial structures and the distances between the epitaxial structures and a gate structure of the MOS transistor etc will affect stresses induced by the epitaxial structures in a gate channel, which affects the speed of the MOS transistor. The structure, type and material properties of the gate paired with the epitaxial structures will also affect the electrical performance.